SH7760 Datasheet, PDF (695/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

19.3.3 Slave Interrupt Enable Register (ICSIER)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
- SSRE SDEE SDTE SDRE SARE
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R R/W R/W R/W R/W R/W
Bit
Bit Name
31 to 5 
Initial Value R/W
All 0
R
4
SSRE
0
R/W
3
SDEE
0
R/W
2
SDTE
0
R/W
1
SDRE
0
R/W
0
SARE
0
R/W
Description
Reserved
These bits are always read as 0, and the write
value should always be 0.
Slave Stop Receive Interrupt Enable
0: The SSR interrupt is disabled
1: The SSR interrupt is enabled
Slave Data Empty Interrupt Enable
0: The SDE interrupt is disabled
1: The SDE interrupt is enabled
Slave Data Transmit Interrupt Enable
0: The SDT interrupt is disabled
1: The SDT interrupt is enabled
Slave Data Receive Interrupt Enable
0: The SDR interrupt is disabled
1: The SDR interrupt is enabled
Slave Address Receive Interrupt Enable
0: The SAR interrupt is disabled
1: The SAR interrupt is enabled
Rev. 1.0, 02/03, page 645 of 1294