SH7760 Datasheet, PDF (527/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

12.5.3 Changing Bus Clock Frequency Division Ratio (When PLL Circuit 2 is On)
If PLL circuit 2 is on when the bus clock frequency division ratio is changed, the oscillation
stabilization time for PLL circuit 2 is required.
1. Make WDT settings as in step 1 in section 12.5.1.
2. Set the BFC2 to BFC0 bits to the desired value.
3. This LSI stops temporarily, and the WDT starts counting up. The internal clock stops and an
unstable clock is output to the CKIO pin.
4. After the WDT count overflows, a clock begins to be supplied within the chip, and this LSI
resumes operation. The WDT stops after overflowing.
12.5.4 Changing Bus Clock Frequency Division Ratio (When PLL Circuit 2 is Off)
If PLL circuit 2 is off when the bus clock frequency division ratio is changed, WDT counting is
not performed.
1. Set the BFC2 to BFC0 bits to the desired value.
2. The specified clock is switched to immediately.
12.5.5 Changing Frequency Division Ratio of CPU Clock or Peripheral Clock
When the frequency division ratio of the CPU clock or peripheral clock is changed, WDT
counting is not performed.
1. Set the IFC2 to IFC0 or PFC2 to PFC0 bits to the desired value.
2. The specified clock is switched to immediately.
12.5.6 Switching between PLL Circuit 3 On/Off
When PLL circuit 3 is turned on, the oscillation stabilization time for PLL circuit 3 is required.
The oscillation stabilization time is counted by an on-chip fixed timer. After counting has finished
(oscillation stabilized), the DCKEN bit in DCKDR is set to 1. At this timing the DCK oscillation
stabilization end can be notified to external devices by using the GPIO to output the value in the
DCKEN bit.
Before turning on/off PLL circuit 1 or 2, changing the bus clock frequency division ratio, or
entering standby mode, make sure to stop PLL circuit 3 (clear the DCKEN bit to 0). After
changing these settings, start PLL circuit 3.
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