SH7760 Datasheet, PDF (909/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Bit Name
9
PK4MD1
8
PK4MD0
7
PK3MD1
6
PK3MD0
5
PK2MD1
4
PK2MD0
3 to 0 
Initial value R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
All 0
R
Description
PTK4 Mode
00: Peripheral module (Reserved/AUD)
01: Port output
10: Port input (pull-up MOS: Off)
11: Port input (pull-up MOS: On)
PTK3 Mode
00: Peripheral module (Reserved/AUD)
01: Port output
10: Port input (pull-up MOS: Off)
11: Port input (pull-up MOS: On)
PTK2 Mode
00: Peripheral module (ADC/AUD)
01: Port output
10: Port input (pull-up MOS: Off)
11: Port input (pull-up MOS: On)
Reserved
These bits are always read as 0, and the write
value should always be 0.
24.2.11 Port A Data Register (PADR)
PADR is an 8-bit readable/writable register that stores port A data.
Bit: 7
6
5
4
3
2
1
0
PA7DT PA6DT PA5DT PA4DT PA3DT PA2DT ^-
-
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R
R
Bit
Bit Name Initial value R/W Description
7
PA7DT
0
6
PA6DT
0
5
PA5DT
0
4
PA4DT
0
3
PA3DT
0
2
PA2DT
0
R/W These bits store output data of a pin which is used
R/W ^{as a general output port. When the pin functions}
as a general output port, if the port is read, the
R/W _{value of this corresponding register will be read}
R/W ^{out. When the pin functions as a general input}
port, if the port is read, the status of the
R/W _{corresponding pin will be read out.}
R/W
1, 0

All 0
R
Reserved
These bits are always read as 0, and the write
value should always be 0.
Rev. 1.0, 02/03, page 859 of 1294