SH7760 Datasheet, PDF (154/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

The area from H'F600 0000 to H'F6FF FFFF is used for direct access to the unified TLB address
array. For details, see section 6.6.4, UTLB Address Array.
The area from H'F700 0000 to H'F7FF FFFF is used for direct access to unified TLB data arrays 1
and 2. For details, see section 6.6.5, UTLB Data Array 1, and section 6.6.6, UTLB Data Array 2.
The area from H'FC00 0000 to H'FFFF FFFF is the on-chip peripheral module control register
area.
(2) External Memory Space
This LSI supports a 29-bit external memory space. The external memory space is divided into
eight areas as shown in figure 6.4. Areas 0 to 6 relate to memory, such as SRAM, synchronous
DRAM, and PCMCIA. Area 7 is a reserved area. For details, see section 10, Bus State Controller
(BSC).
H'0000 0000
H'0400 0000
H'0800 0000
H'0C00 0000
H'1000 0000
H'1400 0000
H'1800 0000
H'1C00 0000
H'1FFF FFFF
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6
Area 7 (reserved area)
Figure 6.4 External Memory Space
Rev. 1.0, 02/03, page 104 of 1294