SH7760 Datasheet, PDF (31/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Figure 10.16 Basic Timing for Synchronous DRAM Burst Read ..............................................304
Figure 10.17 Basic Timing for Synchronous DRAM Single Read.............................................305
Figure 10.18 Basic Timing for Synchronous DRAM Burst Write .............................................306
Figure 10.19 Basic Timing for Synchronous DRAM Single Write ............................................308
Figure 10.20 Burst Read Timing ................................................................................................310
Figure 10.21 Burst Read Timing (RAS Down, Same Row Address) .........................................311
Figure 10.22 Burst Read Timing (RAS Down, Different Row Addresses) ................................312
Figure 10.23 Burst Write Timing................................................................................................313
Figure 10.24 Burst Write Timing (Same Row Address).............................................................314
Figure 10.25 Burst Write Timing (Different Row Addresses)....................................................315
Figure 10.26 Burst Read Cycle for Different Bank and Row Address From Preceding
Burst Read Cycle ...................................................................................................316
Figure 10.27 Auto-Refresh Operation ........................................................................................318
Figure 10.28 Synchronous DRAM Auto-Refresh Timing ..........................................................318
Figure 10.29 Synchronous DRAM Self-Refresh Timing ...........................................................320
Figure 10.30(1) Synchronous DRAM Mode Write Timing (PALL) ..........................................322
Figure 10.30(2) Synchronous DRAM Mode Write Timing (Mode Register Setting) ................323
Figure 10.31 Basic Timing of a Burst Read from Synchronous DRAM (Burst Length = 8)......325
Figure 10.32 Basic Timing of a Burst Write to Synchronous DRAM ........................................326
Figure 10.33 Burst ROM Basic Access Timing .........................................................................328
Figure 10.34 Burst ROM Wait Access Timing...........................................................................329
Figure 10.35 Burst ROM Wait Access Timing...........................................................................330
Figure 10.36 Example of PCMCIA Interface .............................................................................334
Figure 10.37 Basic Timing for PCMCIA Memory Card Interface .............................................335
Figure 10.38 Wait Timing for PCMCIA Memory Card Interface ..............................................336
Figure 10.39 PCMCIA Space Allocation ...................................................................................337
Figure 10.40 Basic Timing for PCMCIA I/O Card Interface .....................................................338
Figure 10.41 Wait Timing for PCMCIA I/O Card Interface.......................................................339
Figure 10.42 Dynamic Bus Sizing Timing for PCMCIA I/O Card Interface .............................340
Figure 10.43 Example of 32-Bit Data Width MPX Connection .................................................341
Figure 10.44 MPX Interface Timing 1 (Single Read Cycle, AnW = 0, No External Wait)........342
Figure 10.45 MPX Interface Timing 2 (Single Read, AnW = 0, One External Wait Inserted) ..343
Figure 10.46 MPX Interface Timing 3 (Single Write Cycle, AnW = 0, No External Wait).......344
Figure 10.47 MPX Interface Timing 4 (Single Write, AnW = 1, One External Wait Inserted) 345
Figure 10.48 MPX Interface Timing 5 (Burst Read Cycle, AnW = 0, No External Wait,
32-Bit Bus Width, 32-Byte Data Transfer)............................................................346
Figure 10.49 MPX Interface Timing 6 (Burst Read Cycle, AnW = 0, External Wait Control,
32-Bit Bus Width, 32-Byte Data Transfer)............................................................346
Figure 10.50 MPX Interface Timing 7 (Burst Write Cycle, AnW = 0, No External Wait,
32-Bit Bus Width, 32-Byte Data Transfer)............................................................347
Figure 10.51 MPX Interface Timing 8 (Burst Write Cycle, AnW = 1, External Wait Control,
32-Bit Bus Width, 32-Byte Data Transfer)............................................................347
Rev. 1.0, 02/03, page xxix of xlviii