SH7760 Datasheet, PDF (227/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

8.5 Operation
8.5.1 Resets
(1) Power-On Reset
• Sources:
 RESET pin low level
 When the watchdog timer overflows while the WT/IT bit is set to 1 and the RSTS bit is
cleared to 0 in WTCSR. For details, see section 13, Watchdog timer (WDT).
• Transition address: H'A000 0000
• Transition operations:
Exception code H'000 is set in EXPEVT, initialization of VBR and SR is performed, and a
branch is made to PC = H'A000 0000.
In the initialization processing, the VBR register is set to H'0000 0000, and in SR, the MD,
RB, and BL bits are set to 1, the FD bit is cleared to 0, and the interrupt mask level bits
(IMASK3 to IMASK0) are set to B'1111.
CPU and on-chip peripheral module initialization is performed. For details, see the register
descriptions in the relevant sections. For some CPU functions, the TRST pin and RESET pin
must be driven low. It is therefore essential to execute a power-on reset and drive the TRST
pin low when powering on.
If the RESET pin is driven high before the MRESET pin while both these pins are low, a
manual reset may occur after the power-on reset operation. The RESET pin must be driven
high at the same time as, or after, the MRESET pin.
Power_on_reset()
{
EXPEVT = H'0000 0000;
VBR = H'0000 0000;
SR.MD = 1;
SR.RB = 1;
SR.BL = 1;
SR.(I0-I3) = B'1111;
SR.FD=0;
Initialize_CPU();
Initialize_Module(PowerOn);
PC = H'A000 0000;
}
Rev. 1.0, 02/03, page 177 of 1294