SH7760 Datasheet, PDF (297/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Initial
Bit
Name Value R/W Description
10
A5BST2 0
9
A5BST1 0
8
A5BST0 0
R/W Area 5 Burst ROM Control
R/W These bits specify whether burst ROM interface is used
R/W in area 5. When burst ROM interface is used, they also
specify the number of accesses in a burst. When area 5
is an MPX interface area, the settings of these bits are
ignored. When area 5 is used as a PCMCIA area, these
bits should be cleared to 0.
000: Area 5 is accessed as SRAM interface.
001: Area 5 is accessed as burst ROM interface
(4 consecutive accesses). Can be used with 8-, 16-,
or 32-bit bus width
010: Area 5 is accessed as burst ROM interface
(8 consecutive accesses). Can be used with 8-, 16-,
or 32-bit bus width
011: Area 5 is accessed as burst ROM interface
(16 consecutive accesses). Can only be used with
8- or 16-bit bus width. The setting of 32-bit bus width
is prohibited.
100: Area 5 is accessed as burst ROM interface
(32 consecutive accesses). Can only be used with
8-bit bus width
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
Rev. 1.0, 02/03, page 247 of 1294