SH7760 Datasheet, PDF (357/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

(6) Single Write
The basic timing chart for single write access is shown in figure 10.19. In a single write
operation, a WRITA command that performs auto-precharge is issued in cycle Tc1 following
the Tr cycle where the ACTV command is output. In the write cycle, the write data is output at
the same time as the write command. For the write with auto-precharge command, precharging
of the relevant bank is performed in the synchronous DRAM after completion of the write
command, and therefore no command can be issued for the synchronous DRAM until
precharging is completed. Consequently, in addition to the precharge wait cycle Tpc used in a
read access, cycle Trwl is also added as a wait cycle until precharging is started following the
write command for delaying issuance of a new command for the synchronous DRAM during
this period. Bits TRWL2 to TRWL0 in MCR can be used to specify the number of Trwl cycles.
DACK is asserted two cycles before the data write cycle.
This LSI supports 4- or 8-burst-length read and write operations of synchronous DRAM.
Dummy cycles are therefore generated even with single write operations.
Rev. 1.0, 02/03, page 307 of 1294