SH7760 Datasheet, PDF (338/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

The setup time of the address and CS signal with respect to the read/write strobe can be
specified by bit A1S0 in WCR3 within a range of 0 to 1 cycle. The data-hold time of the
address and CS signal with respect to the read/write strobe can be specified by bits A1H1 and
A1H0 within a range of 0 to 3 cycles.
(3) Area 2
For area 2, off-chip address bits A28 to A26 are 010.
The interfaces that can be set for this area are SRAM, MPX, and synchronous DRAM.
When the SRAM interface is in use, a bus width of 8, 16, or 32 bits is selectable with bits
A2SZ1 and A2SZ0 in BCR2. When the MPX interface is in use, a bus width of 32 bits should
be selected by bits A2SZ1 and A2SZ0 in BCR2. When the synchronous DRAM interface is in
use, select 32 bits by the SZ bits in MCR.
When area 2 is accessed, the CS2 signal is asserted. When the SRAM interface is in use, the
RD signal, which can be used as OE, and write control signals WE0 to WE3 are asserted.
As regards the number of bus cycles, 0 to 15 wait cycles is selectable with bits A2W2 to
A2W0 in WCR2. In addition, any number of wait cycles can be inserted in each bus cycle by
the external wait pin (RDY).
The setup time of the address and CS signal with respect to the read/write strobe can be
specified by bit A2S0 in WCR3 within a range of 0 to 1 cycle. The data-hold time of the
address and CS signal with respect to the read/write strobe can be specified by bits A2H1 and
A2H0 within a range of 0 to 3 cycles.
When the synchronous DRAM interface is in use, the RAS, CAS, and RD/WR signals and
byte control signals DQM0 to DQM3 are asserted, and address multiplexing is performed.
Timing control for signals RAS, CAS, and data, and address multiplexing control, can be
specified by MCR.
(4) Area 3
For area 3, off-chip address bits A28 to A26 are 011.
The interfaces that can be set for this area are SRAM, MPX, and synchronous DRAM.
When the SRAM interface is in use, a bus width of 8, 16, or 32 bits is selectable with bits
A3SZ1 and A3SZ0 in BCR2. When the MPX interface is in use, a bus width of 32 bits should
be selected by bits A3SZ1 and A3SZ0 in BCR2. When the synchronous DRAM interface is in
use, select 32 bits by the SZ bits in MCR.
When area 3 is accessed, the CS3 signal is asserted. When the SRAM interface is in use, the
RD signal, which can be used as OE, and write control signals WE0 to WE3 are asserted.
Rev. 1.0, 02/03, page 288 of 1294