SH7760 Datasheet, PDF (782/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

21.3.7 Host Controller Communication Area Pointer Register (HcHCCA)
HcHCCA stores physical addresses of the host controller communication area (HCCA). HCD
determines the alignment restrictions by writing 1 to all bits in HcHCCA and by reading the
contents of HcHCCA. Alignment is evaluated by checking the number of 0s in the low-order bits.
The minimum alignment is 256 bytes. Consequently, bits 0 to 7 must always return 0 when they
are read. This area is used to retain the control structures and interrupt table that are accessed by
HC and HCD.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HCCA
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
HCCA
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R R
Bits
31 to 8
7 to 0
Bit Name
HCCA

Initial Value R/W
All 0
R/W
All 0
R
Description
Host Controller Communication Area Address
These bits store the base address of HCCA.
Reserved
These bits are always read as 0. Always write 0 to
this bit.
21.3.8 Period Current ED Pointer Register (HcPeriodCurrentED)
HcPeriodCurrentED stores the address of the isochronous ED or interrupt ED to be processed in
the current frame.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PCED
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
PCED
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Rev. 1.0, 02/03, page 732 of 1294