SH7760 Datasheet, PDF (267/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

9.4 Interrupt Sources
There are four types of interrupt sources: NMI, IRQ, IRL, and peripheral modules. Each interrupt
has a priority level (16 to 0), with level 16 as the highest and level 1 as the lowest. When level 0 is
set, the interrupt is masked and interrupt requests are ignored.
9.4.1 NMI Interrupt
The NMI interrupt has the highest priority level of 16. It is always accepted unless the BL bit in
SR of the CPU is set to 1. In sleep or standby mode, the interrupt is accepted even if the BL bit is
set to 1.
A setting can also be made to have the NMI interrupt accepted even if the BL bit is set to 1.
Input from the NMI pin is edge-detected. The NMI edge select bit (NMIE) in ICR is used to select
either rising or falling edge as the detection edge. When the NMIE bit in ICR is modified, the
NMI interrupt is not detected for a maximum of six bus clock cycles after the modification.
NMI interrupt exception handling does not affect the interrupt mask level bits (IMASK3 to
IMASK0) in SR.
9.4.2 IRQ Interrupts
IRQ interrupts are input by level at pins IRQ7 to IRQ4. After an IRQ interrupt is accepted, the pin
level must be retained until the interrupt processing starts.
9.4.3 IRL Interrupts
IRL interrupts are input by level at pins IRL3 to IRL0.
The priority level is the level indicated by pins IRL3 to IRL0. An IRL3 to IRL0 value of 0 (0000)
indicates the highest-level interrupt request (interrupt priority level 15). A value of 15 (1111)
indicates no interrupt request (interrupt priority level 0). Figure 9.2 shows an example of IRL
interrupt connection, and table 9.6 shows the correspondence between the IRL pins and interrupt
levels.
Rev. 1.0, 02/03, page 217 of 1294