SH7760 Datasheet, PDF (928/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Bit Name
11
IPSELR11
10
IPSELR10
9
IPSELR9
8 to 2 —
1
LCDMD1
0
LCDMD0
Initial Value
0
0
0
All 0
1
1
R/W Description
R/W Out of the modules SSI[1]/[0] and HAC[1]/[0], select
R/W ^{the one using the pins}
SSI0_SCK/HAC_SD_IN0/BS2,
SSI0_WS/HAC_SYNC0,
SSI0_SDATA/HAC_SD_OUT0,
SSI1_SCK/HAC_SD_IN1,
SSI1_SDATA/HAC_SD_OUT1, and
SSI1_WS/HAC_SYNC1.
00: SSI[0], SSI[1]
01: HAC[0]. SSI[1]
10:Setting prohibited
11:HAC[0], HAC[1]
R/W Select the pins MFI-D8/LCD_DATA8 to MFI-
D15/LCD_DATA15 of MFI/LCDC.
0: MFI/LCDC
1: Setting prohibited
R Reserved
These bits are always read as 0, and the write value
should always be 0.
R/W LDCD mode settings
R/W 00: Mode 1 LCD_CL1 and LCD_FLM output
LCD_CL2 output
01: Mode 2 LCD_CL1 and LCD_FLM output
LCD_CL2 Hiz
Other than above: Setting prohibited
Note: When using the LCDC, be sure to set these
bits to B'00 or B'01.
24.2.36 SCIF.Hi-z Control Register (SCIHZR)
SCIHZR is a 16-bit readable/writable register that controls the pin state of the individual port pins
in software standby mode when a Peripheral module (SCIF0 to SCIF2) is selected by the PGCR or
PHCR. When each bit is 0, the corresponding pin retains the state before the software standby
mode is entered. This register settings is ignored when the pins are specified as the GPIO port by
PGCR or PHCR. This register setting is also ignored when the SCIF controls the pins.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
SCI SCI SCI SCI SCI SCI SCI SCI SCI SCI SCI SCI SCI
-
-
-
CLK0 RXD0 TXD0 CLK1 CTS1 RTS1 RXD1 TXD1 CLK2 CTS2 RTS2 RXD2 TXD2
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R
R
R
Rev. 1.0, 02/03, page 878 of 1294