SH7760 Datasheet, PDF (508/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

11.6.11 LCDC DMA Transfer
Figure 11.38 shows a DMA transfer flow for the LCDC.
Transfer start
Set DMAC registers
Set LCDC registers
DMA transfer
[1] Set DMAOR, DMATCR0, and DMARSRA so that
DMABRG can be used.
[1]
[2] Set LCDC registers. For details of LCDC register
settings, see section 30, LCDC Controller (LCDC).
[3] DMA transfer is started by a DMA transfer request
[2]
output from the LCDC. Data in synchronous DRAM
is stored in FIFO of DMABRG.
[4] The data stored in FIFO is transmitted to the LCDC.
[5] DMA transfer is repeated until the DMA transfer
request from the LCDC is stopped.
Data stored in FIFO
[3]
Data transferred to LCDC
[4]
No
Has transfer completed?
[5]
Yes
Transfer end
Figure 11.38 Example of LCDC Data Transfer Flow
11.6.12 USB DMA Transfer
The USB contains a 8-kbyte shared memory. It is possible to perform a DMA transfer between the
USB internal shared memory and synchronous DRAM by using the DMABRG.
Figure 11.39 shows a DMA transfer flow between the shared memory and synchronous DRAM.
On this transfer, specifying the transfer size and number of transfers is not needed. The DMABRG
converts the number of transfer bytes specified by the SZ bits in DMAURWSZ into the
appropriate transfer data size and the number of transfers to perform a DMA transfer. When the
number of bytes actually transferred reaches the number of transfer bytes specified by the SZ bits
in DMAURWSZ, the UTF bit in DMABRGCR is set to 1 and the DMA transfer is successfully
completed.
When the transfer is continued beyond the shared memory area (H’FE34 1000 to H’FE34 2FFF), a
USB address error is generated. When a USB address error is detected, the UAF bit in
DMABRGCR is set to 1 and operation ends abnormally.
Rev. 1.0, 02/03, page 458 of 1294