SH7760 Datasheet, PDF (625/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

17.3.14 Serial Error Register (SCRER)
SCRER is a 16-bit register that indicates the number of receive errors in the data in SCFRDR.
SCRER can always be read from the CPU.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
PER7 PER6 PER5 PER4 PER3 PER2 PER1 PER0 FER7 FER6 FER5 FER4 FER3 FER2 FER1 FER0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit
Bit Name Initial Value R/W Description
15
PER7
0
14
PER6
0
13
PER5
0
12
PER4
0
11
PER3
0
10
PER2
0
9
PER1
0
8
PER0
0
R
Number of Parity Errors
R
These bits indicate the number of data bytes in
R
which a parity error occurred in the receive data
R
stored in SCFRDR.
R
After the ER bit in SCFSR is set, the value
R
indicated by bits PER7 to PER0 is the number of
R
data bytes in which a parity error occurred.
R
If all 128 bytes of receive data in SCFRDR have
parity errors, the value indicated by bits PER7 to
PER0 will be 0.
7
FER7
0
6
FER6
0
5
FER5
0
4
FER4
0
3
FER3
0
2
FER2
0
1
FER1
0
0
FER0
0
R
Number of Framing Errors
R
These bits indicate the number of data bytes in
R
which a framing error occurred in the receive data
R
stored in SCFRDR.
R
After the ER bit in SCFSR is set, the value
R
indicated by bits FER7 to FER0 is the number of
R
data bytes in which a framing error occurred.
R
If all 128 bytes of receive data in SCFRDR have
framing errors, the value indicated by bits FER7 to
FER0 will be 0.
Rev. 1.0, 02/03, page 575 of 1294