SH7760 Datasheet, PDF (264/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

• INTMSK00
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value: 1
1
1
1
0
R/W: R/W R/W R/W R/W R
Bit: 15 14 13 12 11
0
1
1
1
1
1
1
1
1
1
1
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
10 9
8
7
6
5
4
3
2
1
0
Initial value: 0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W: R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name
31 to 28
27, 26
25 to 16
15
14 to 0
Initial Value R/W
All 1
R/W
All 0
R
All 1
R/W
0
R
All 1
R/W
Description
Interrupt Masks 31 to 28
These bits set the masking of the interrupt
request that corresponds to the given bit. For the
correspondence between bits and interrupt
sources, see table 9.5.
0: Corresponding interrupt requests are accepted
1: Corresponding interrupt requests are masked
Reserved
These bits are always read as 0. The write value
should always be 0.
Interrupt Masks 25 to 16
These bits set the masking of the interrupt
request that corresponds to the given bit. For the
correspondence between bits and interrupt
sources, see table 9.5.
0: Corresponding interrupt requests are accepted
1: Corresponding interrupt requests are masked
Reserved
This bit is always read as 0. The write value
should always be 0.
Interrupt Masks 14 to 0
These bits set the masking of the interrupt
request that corresponds to the given bit. For the
correspondence between bits and interrupt
sources, see table 9.5.
0: Corresponding interrupt requests are accepted
1: Corresponding interrupt requests are masked
Rev. 1.0, 02/03, page 214 of 1294