SH7760 Datasheet, PDF (843/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Bit Name Initial Value R/W Description
6
IRR6
0
R/W Bus Off Interrupt Flag
This bit is set when the HCAN2 enters the Bus-off
state or when the HCAN2 leaves Bus-off state
and returns to Error-Active. This is because that
the existing condition is that 11 recessive bits x
128 have been received at the node of TEC ≥ 256
or at the end of Bus-off. This bit remains latched
even though the HCAN2 node leaves the Bus-off
condition, and needs to be explicitly cleared by
software. The software is expected to read the
GSR0 to judge whether HCAN2 has become Bus-
off or error active, GSR0 should be read. This bit
is cleared by writing a 1. Writing a 0 has no effect.
0: Clearing condition: Write a 1 to this bit.
1: Bus off state caused by a transmit error or error
active state returned from Bus-off.
Setting condition: TEC ≥ 256 or the end of bus-
off after receiving 128 x 11 bits
5
IRR5
0
R/W Error Passive Interrupt Flag
Indicates the Error Passive state caused by the
transmit/receive error counter. This bit is cleared
by writing a 1, while writing a 0 has no effect. If
this bit is cleared, the node may still be error
passive.
0: Clearing condition: Write a 1 to this bit.
1: Error passive state is caused by a
transmit/receive error.
Setting condition: TEC ≥ 128 or REC ≥ 128
4
IRR4
0
R/W Receive Overload Warning Interrupt Flag
This bit becomes set and latches if the receive
error counter (REC) reaches a value greater than
96. This bit is cleared by writing a 1. Writing a 0
has no effect. When the interrupt is cleared, the
REC still holds its value greater than 96.
0: Clearing condition: Write a 1 to this bit.
1: Error warning state is caused by a receive
error. Setting condition: REC ≥ 96
Rev. 1.0, 02/03, page 793 of 1294