SH7760 Datasheet, PDF (252/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

8.7 Restrictions
8.7.1 Restrictions on First Instruction in Exception Handling Routine
• Do not locate a BT, BF, BT/S, BF/S, BRA, or BSR instruction at address VBR + H'100, VBR
+ H'400, or VBR + H'600.
• When the UBDE bit in BRCR is set to 1 and the user break debug support function is used, do
not locate a BT, BF, BT/S, BF/S, BRA, or BSR instruction at the address indicated by DBR.
Rev. 1.0, 02/03, page 202 of 1294