SH7760 Datasheet, PDF (645/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

(6) Simultaneous Serial Data Transmission and Reception (Synchronous Mode)
Figure 17.21 shows a sample flowchart for simultaneous serial data transmission and
reception.
Use the following procedure for simultaneous serial transmission and reception after enabling
the SCIF for both transmission and reception.
Initialization
[1]
Start of transmission and reception
Read TDFE flag in SCFSR
[2]
No
TDFE = 1?
Yes
Write transmit data to SCFTDR,
and clear TDFE flag
in SCFSR to 0
Read ORER flag in SCLSR
ORER = 1?
No
Read RDF flag in SCFSR
No
RDF = 1?
Yes
Read receive data in
SCFRDR, and clear RDF
flag in SCFSR to 0
No
All data received?
Yes
[3]
Error handling
[4]
[1] SCIF initialization:
See Sample SCIF Initialization
Flowchart in figure 17.16.
[2] SCIF status check and transmit data
write:
Read SCFSR and check that the
TDFE flag is set to 1, then write
transmit data to SCFTDR, and clear
the TDFE flag to 0. The transition of
the TDFE flag from 0 to 1 can also be
identified by a TXI interrupt.
[3] Receive error handling:
Read the ORER flag in SCLSR to
identify any error, perform the
appropriate error handling, then clear
the ORER flag to 0. Reception cannot
be resumed while the ORER flag is
set to 1.
[4] SCIF status check and receive data
read:
Read SCFSR and check that RDF =
1, then read the receive data in
SCFRDR, and clear the RDF flag to
0. The transition of the RDF flag from
0 to 1 can also be identified by an RXI
interrupt.
[5] Serial transmission and reception
continuation procedure:
To continue serial transmission and
reception, read RDF flag and
SCFRDR, and clear the RDF flag to 0
before receiving the MSB in the
current frame. Similarly, read 1 from
the TDFE flag to confirm that writing
is possible before transmitting the
MSB in the current frame. Then write
data to SCFTDR and clear the TDFE
flag to 0.
Yes
Clear TE and RE bits
in SCSCR to 0
[5]
End of transmission and reception
Note: When switching from a transmit operation
or receive operation to simultaneous
transmission and reception operations,
clear the TE and RE bits to 0, and then
set them simultaneously to 1.
Figure 17.21 Sample Simultaneous Serial Transmission and Reception Flowchart
Rev. 1.0, 02/03, page 595 of 1294