SH7760 Datasheet, PDF (299/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Initial
Bit
Name Value R/W Description
4
DRAMTP2 0
3
DRAMTP1 0
2
DRAMTP0 0
R/W Areas 2 and 3 Memory Type
R/W These bits specify the type of memory connected to
R/W areas 2 and 3. Memory types such as ROM, SRAM, and
flash ROM can be connected as an SRAM interface.
Synchronous DRAM can also be connected.
000: Areas 2 and 3 are accessed as an SRAM interface
or MPX interface*
001: Setting prohibited
010: Area 2 is accessed as an SRAM interface or MPX
interface* and area 3 as a synchronous DRAM
interface
011: Areas 2 and 3 are accessed as a synchronous
DRAM interface
100: Setting prohibited
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
Note: * The MEMMPX bit setting selects the SRAM
interface or MPX interface.
1

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
0
A56PCM 0
R/W Area 5 and 6 Bus Type
Specifies whether areas 5 and 6 are accessed as
PCMCIA interface. The setting of this bit has priority over
the MEMMPX bit. When this bit is 1, the MD3 pin is
designated for output as the CE2A pin, and the MD4 pin
is designated for output as the CE2B pin.
0: Areas 5 and 6 are accessed as SRAM interface
1: Areas 5 and 6 are accessed as PCMCIA interface
10.5.2 Bus Control Register 2 (BCR2)
BCR2 is a 16-bit readable/writable register that specifies the bus width for each area and whether
the GPIO interrupt is used.
Do not access off-chip memory space other than area 0 until register initialization is complete.
Rev. 1.0, 02/03, page 249 of 1294