SH7760 Datasheet, PDF (797/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

bit 0 for example, the bit name is CCS and the bit title in read is Current Connect Status, while
that in write is Clear Port Enable.
• Read
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
- PRSC OCIC PSSC PESC CSC
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
- LSDA PPS -
-
- PRS POCI PSS PES CCS
Initial value: 0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit
Bit Name Initial Value
31 to 21 
All 0
20
PRSC
0
19
OCIC
0
18
PSSC
0
17
PESC
0
R/W Description
R
Reserved
These bits are always read as 0.
R
Port Reset Status Change
This bit is set to 1 at the end of the 10-ms port reset
signal.
0: Port reset is not complete
1: Port reset is complete
R
Overcurrent Indicator Change
This bit is valid only if overcurrent conditions are
reported on a per-port basis. This bit is set when
root hub changes the POCI bit.
0: POCI has not changed
1: POCI has changed
R
Port Suspend Status Change
This bit is set to 1 when the full resume sequence
has been completed. This sequence includes the
20-ms resume pulse, LS EOP, and 3-ms
resychronization delay.
0: Port resume is incomplete, or PRSC bit is set to 1
1: Port resume is complete
R
Port Enable Status Change
This bit is set to 1 when a hardware event clears the
PES bit to 0. Writing 1 by HCD does not set this bit
to 1.
0: PES has not changed
1: PES has changed
Rev. 1.0, 02/03, page 747 of 1294