SH7760 Datasheet, PDF (1017/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

CPU
Start transfer-ready
MMCIF
Set DMAC-related
condition
Set DMACR
(DMA enable on)
FIFO ready interrupt
processing
DMA request assert
No
Higher than
specified capacity?
Yes
DMAC
DMAC initiation
Write to FIFO
DMA transfer end?
No
Yes
DMA transfer-end
interrupt processing
Start transfer
No
DMA enable?
Yes
DMA request
No
assert condition?
Yes
DMA request assert
Transfer-end
interrupt processing
No
Transfer end?
Yes
FIFO data amount
Start specified capacity
Assert condition
End
Figure 26.23 Example of Write Sequence Flow
Rev. 1.0, 02/03, page 967 of 1294