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SH7760 Datasheet, PDF (705/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine
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• Receive Data Register (ICRXD) (FIFO Buffer Mode)
ICRXD is a 16-stage FIFO register for storing the receive data. When 1-byte data is received,
the receive data is transferred to ICRXD from the shift register, and reception ends. After that,
the ICRXD is ready to receive and consecutive receive operations of up to 16 bytes of data are
possible. When 16 bytes of receive data are stored, the FIFO receive register is full.
ICRXD is read only and cannot be written to by the CPU. When the receive FIFO register is
completely empty, reading ICRXD will return an undefined value. When the receive FIFO
register is full, the subsequent data is lost.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
RXD
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
• Transmit Data Register (ICTXD) (FIFO Buffer Mode)
ICTXD is a 16-stage FIFO register for storing the transmit data. When the data is written to the
ICTXD and the shift register is empty, the data is transferred from ICTXD to the shift register
and transmission starts.
ICTXD is write only and cannot be read from by the CPU. When the register is full with 16
bytes of data, the subsequent data cannot be written to, and the written value is ignored.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W: W W W W W W W W W W W W W W W W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
TXD
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W: W W W W W W W W W W W W W W W W
19.3.11 FIFO Control Register (ICFCR)
ICFCR is a register for resetting the byte count and setting the number of trigger data in transmit
and receive FIFO registers, respectively. ICFCR can always be read from and written to by the
CPU.
Rev. 1.0, 02/03, page 655 of 1294
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