SH7760 Datasheet, PDF (147/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Functional
Category No. Instruction
Instruc-
Lock
tion Issue
Execution
Group Rate Latency Pattern Stage Start Cycles
Double- 210
precision ₂₁₁
floating-point
instructions
FNEG
FSQRT
DRn
DRn
LS
10
#1
FE
1 (23, 24)/ #41
25
———
F3 2 22
F1 21 3
F1 2 2
212 FSUB
DRm,DRn
FE
1 (7, 8)/9 #39
F1 2 6
213 FTRC
DRm,FPUL
FE
1 4/5
#38
F1 2 2
FPU system 214 LDS
Rm,FPUL
LS
11
#1
control
215 LDS
Rm,FPSCR
CO 1 4
#32
instructions
216 LDS.L
@Rm+,FPUL
CO
1
1/2
#2
———
F1 3 3
———
217 LDS.L @Rm+,FPSCR CO 1 1/4
#33
F1 3 3
218 STS
FPUL,Rn
LS
13
#1
———
219 STS
FPSCR,Rn
CO 1 3
#1
———
220 STS.L FPUL,@-Rn
CO 1 1/1
#2
———
221 STS.L FPSCR,@-Rn CO 1 1/1
#2
———
Graphics 222
acceleration ₂₂₃
instructions
224
FMOV
FMOV
FMOV
DRm,XDn
XDm,DRn
XDm,XDn
LS
10
#1
———
LS
10
#1
———
LS
10
#1
———
225 FMOV @Rm,XDn
LS
12
#2
———
226 FMOV @Rm+,XDn
LS
1 1/2
#2
———
227 FMOV @(R0,Rm),XDn LS
12
#2
———
228 FMOV XDm,@Rn
LS
11
#2
———
229 FMOV XDm,@-Rm
LS
1 1/1
#2
———
230 FMOV XDm,@(R0,Rn) LS
11
#2
———
231 FIPR
FVm,FVn
FE
1 4/5
#42
F1 3 1
232 FRCHG
FE
1 1/4
#36
———
233 FSCHG
FE
1 1/4
#36
———
234 FTRV
XMTRX,FVn
FE
1 (5, 5, 6, #43
7)/8
F0 2 4
F1 3 4
Notes: 1. See table 5.1 for the instruction groups.
2. Latency "L1/L2... ": Latency corresponding to a write to each register, including
MACH/MACL/FPSCR.
Example: MOV.B @Rm+, Rn "1/2": Latency for Rm is 1 cycle and latency for Rn is 2
cycles.
3. Branch latency: Interval until the branch destination instruction is fetched
4. Conditional branch latency "2 (or 1) ": Latency is 2 for a non-zero displacement, and 1
for a zero displacement.
5. Double-precision floating-point instruction latency " (L1, L2)/L3": L1 is the latency for FR
[n+1], L2 that for FR [n], and L3 that for FPSCR.
Rev. 1.0, 02/03, page 97 of 1294