SH7760 Datasheet, PDF (447/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

11.3.14 DMA Audio Control Register (DMAACR)
DMAACR is a 32-bit readable/writable register that specifies the DMA operating mode of the
HAC or SSI codec. DMAACR0 corresponds to HAC(0) or SSI(0) and DMAACR1 corresponds to
HAC(1) or SSI(1).
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
- RAM1 RAM0 -
-
-
-
- RAR RDS RDE
Initial value: 0
0
0
0
0
00
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R R/W R/W R
R
R
R
R R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
- TAM1 TAM0 -
-
-
-
- TAR TDS TDE
Initial value: 0
0
0
0
0
00
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R R/W R/W R
R
R
R
R R/W R/W R/W
Bit
Bit Name
31 to 26 
25
RAM1
24
RAM0
23 to 19 
18
RAR
Initial Value R/W
All 0
R
0
R/W
0
R/W
All 0
R
0
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Receive Data Alignment Setting
These bits specify the data alignment method for
writing receive data to an external memory. For
details of the data alignment method for the
receive slot data and external bus, see table 11.5
(1).
00: Alignment control is not performed
01: Longword data is transferred as four byte-data
10: Longword data is transferred as two word-data
11: Setting prohibited
Reserved
These bits are always read as 0. The write value
should always be 0.
DMA Auto Reload Setting
Specifies the use or unuse of auto address reload
to continue a DMA transfer when the number of
bytes in the receive DMA transfer reaches the
number of transfer bytes specified by
DMAARXTCRn.
0: Address of receive DMA not auto reloaded
1: Address of receive DMA auto reloaded
Rev. 1.0, 02/03, page 397 of 1294