SH7760 Datasheet, PDF (1274/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

CKIO
Bank
Precharge-sel
Tr
Trw
Tc1
Tc2
Tc3
Tc4
Tc5
Tc6
Tc7
Tc8
Trw1
Trw1
t_AD
Row
Row
t_AD
H/L
t_AD
t_AD
H/L
Address
CSn
RD/WR
RAS
CASS
DQMn
D31-D0
(write)
BS
Row
c1
c5
t_CSD
t_RWD t_RWD
t_RASD t_RASD
t_CASD2 t_CASD2
t_CSD
t_DQMD
t_DQMD
t_WDD
t_WDD
c1
c2
c3
c4
c5
c6
c7
c8
t_BSD
t_BSD
CKE
DACKn
(SA: IO memory)
t_DACD
t_DACD
NOTES: IO : Dack device
SA : Single address DMA transfer
DA: Dual address DMA transfer
DACK set to active-high
Figure 33.32 Synchronous DRAM Normal Write Bus Cycle: ACT+WRITE Commands,
Burst (RCD[1:0]=01, TRWL[2:0]=010)
Rev. 1.0, 02/03, page 1224 of 1294