SH7760 Datasheet, PDF (363/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

CKIO
Bank
Precharge-sel
Address
CSn
RD/WR
RAS
CASS
DQMn
Tr Trw Tc1 Tc2 Tc3 Tc4 Tc5 Tc6 Tc7 Tc8 Trw1 Trw1
Row
Row
Row
H/L
c1
H/L
c5
D31–D0
(write)
BS
CKE
DACKn
(SA: IO → memory)
c1 c2 c3 c4 c5 c6 c7 c8
Note: For DACKn, an example is shown where CHCRn.AL (acknowledge level) = 0 for the DMAC.
Figure 10.23 Burst Write Timing
Rev. 1.0, 02/03, page 313 of 1294