SH7760 Datasheet, PDF (1087/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

30.3 Register Configuration
The LCDC includes the following registers. For description on the address and processing status
of these registers, refer to section 32, List of Registers.
Table 30.2 Register Configuration (1)
Register Name
Abbrev. R/W
LCDC input clock register
LDICKR R/W
LCDC module type register
LDMTR R/W
LCDC data format register
LDDFR R/W
LCDC scan mode register
LDSMR R/W
LCDC display start address register - LDSARU R/W
upper
LCDC display start address register - LDSARL R/W
lower
LCDC display line address offset
register
LDLAOR R/W
LCDC palette control register
LDPALCR R/W
Palette data registers 00 to FF
LDPR00 to R/W
FF*¹
LCDC horizontal character number LDHCNR R/W
register
LCDC horizontal synchronization
signal register
LDHSYNR R/W
LCDC vertical display line number LDVDLNR R/W
register
LCDC vertical total line number
register
LDVTLNR R/W
LCDC vertical synchronization signal LDVSYNR R/W
register
LCDC AC modulation signal toggle LDACLNR R/W
line number register
LCDC interrupt control register
LDINTR R/W
LCDC power management mode
register
LDPMMR R/W
LCDC power supply sequence period LDPSPR R/W
register
LCDC control register
LDCNTR R/W
P4 Address
H’FE30 0C00
H’FE30 0C02
H’FE30 0C04
H’FE30 0C06
H’FE30 0C08
H’FE30 0C0C
H’FE30 0C10
H’FE30 0C12
H’FE30 0800
H’FE30 0C14
H’FE30 0C16
H’FE30 0C18
H’FE30 0C1A
H’FE30 0C1C
H’FE30 0C1E
H’FE30 0C20
H’FE30 0C24
H’FE30 0C26
H’FE30 0C28
Area 7 Address Size
H’1E30 0C00 16
H’1E30 0C02 16
H’1E30 0C04 16
H’1E30 0C06 16
H’1E30 0C08 32
Sync
Clock
Pck
Pck
Pck
Pck
Pck
H’1E30 0C0C 32 Pck
H’1E30 0C10 16 Pck
H’1E30 0C12 16 Pck
H’1E30 0800 32 Pck
H’1E30 0C14 16 Pck
H’1E30 0C16 16 Pck
H’1E30 0C18 16 Pck
H’1E30 0C1A 16 Pck
H’1E30 0C1C 16 Pck
H’1E30 0C1E 16 Pck
H’1E30 0C20 16 Pck
H’1E30 0C24 16 Pck
H’1E30 0C26 16 Pck
H’1E30 0C28 16 Pck
Rev. 1.0, 02/03, page 1037 of 1294