SH7760 Datasheet, PDF (781/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bits Bit Name
31
MIE
30
OC
29 to 7 
6
RHSC
5
FNO
4
UE
3
RD
2
SF
1
WDH
0
SO
Initial Value R/W
0
R/W
0
R/W
All 0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Description
Master Interrupt Enable
0: Operation is not affected
1: Interrupt generation for other events is disabled
Ownership Change
0: Operation is not affected
1: Interrupt generation for HC control change is
disabled
Reserved
These bits are always read as 0. Always write 0 to
this bit.
Root Hub Status Change
0: Operation is not affected
1: Interrupt generation due to Root Hub Status
Change is disabled
Frame Number Overflow
0: Operation is not affected
1: Interrupt generation due to Frame Number
Overflow is disabled
Unrecoverable Error
0: Operation is not affected
1: Interrupt generation due to unrecoverable error is
disabled
Resume Detected
0: Operation is not affected
1: Interrupt generation due to Resume Detected is
disabled
Start of Frame
0: Operation is not affected
1: Interrupt generation due to Start of Frame is
disabled
Writeback Done Head
0: Operation is not affected
1: Interrupt generation due to HcDonehead
Writeback is disabled
Scheduling Overrun
0: Operation is not affected
1: Interrupt generation due to Scheduling Overrun is
disabled
Rev. 1.0, 02/03, page 731 of 1294