SH7760 Datasheet, PDF (1162/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

 Channel B: ASID: H'70 / address: H'0003 1415 / address mask: H'00
Data: H'0000 0000 / data mask: H'0000 0000
Bus cycle: CPU, instruction access (pre-instruction-execution), read (operand size not
included in conditions)
A user break interrupt is not generated on channel A since the instruction access is not a write
cycle.
A user break interrupt is not generated on channel B since instruction access is performed on
an even address.
(2) Operand Access Cycle Break Condition Settings
1. Register settings: BASRA = H'80 / BARA = H'0012 3456 / BAMRA = H'00 /
BBRA = H'0024 / BASRB = H'70/ BARB = H'000A BCDE / BAMRB = H'02 /
BBRB = H'002A / BDRB = H'0000 A512 / BDMRB = H'0000 0000 / BRCR = H'0080
• Conditions set: Independent channel A/channel B mode
 Channel A: ASID: H'80 / address: H'0012 3456 / address mask: H'00
Bus cycle: operand access, read (operand size not included in conditions)
 Channel B: ASID: H'70 / address: H'000A BCDE / address mask: H'02
Data: H'0000 A512 / data mask: H'0000 0000
Bus cycle: operand access, write, word
Data break enabled
On channel A, a user break interrupt is generated in the event of a longword read at address
H'0012 3454, a word read at address H'0012 3456, or a byte read at address H'0012 3456, with
ASID = H'80.
On channel B, a user break interrupt is generated when H'A512 is written by word access to
any address from H'000A B000 to H'000A BFFE with ASID = H'70.
Rev. 1.0, 02/03, page 1112 of 1294