SH7760 Datasheet, PDF (591/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

16.4.7 Counter: Up-Counter with Capture
In this mode, the 16-bit counter of channel 2 will operate either as a free-running up-counter or as
an up-counter with input capture, depending on the setting of the FRCM bit. If the FRCM bit is
cleared to 0, the counter counts up when an active edge is detected on the input pin of channel 3. If
the FRCM bit is set to 1, the counter is a free-running counter. The counter will retain its value or
can be cleared to H'0000 by disabling the timer enable bit.
IRQ
CMT_CTR _{Pin A Edge detection}
Read
Channel time register
CMT_CTR _{Pin B}
Edge detection
MPX
Up-counter
Internal clock
FRCM
Preload
Figure 16.10 Up-Counter with Capture Mode
16.4.8 Interrupts
The Status Register will have the interrupt status bits set for timer operation on either input
capture or output compare regardless of the state of the interrupt enable bits. The counters will set
an interrupt status bit if the count changes or the counter underflows or overflows. If the interrupt
enable bit for a type of interrupt and the interrupt status bit of the same type for the same channel
is set then an interrupt is generated.
Rev. 1.0, 02/03, page 541 of 1294