SH7760 Datasheet, PDF (422/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Notes: 1. Make the setting of bit 0, bits 1 and 0, bits 2 to 0, or bits 4 to 0 to match the boundary
when specifying a 16-bit, 32-bit, 64-bit, or 32-byte boundary address, respectively. If
an address is specified regardless of the boundary, an address error will be detected and
the DMAC stops operation on all channels (AE (address error flag) bit in DMAOR is
1). The DMAC will also detect an address error and stop operation if an area 7 address
is specified for a data transfer via the external bus or if an address for an on-chip
peripheral module that does not exist is specified.
2. An external address is 29 bits long. Bits 31 to 29 in both SAR and DAR are not used in
DMA transfers. Therefore, clearing bits 31 to 29 to 0 in both SAR and DAR is
recommended.
11.3.3 DMA Transfer Count Register (DMATCR)
DMATCR is a 32-bit readable/writable register that specifies the transfer count for the
corresponding channel. Specifying H'0000 0001 gives a transfer count of 1, while H'0000 0000
gives the maximum setting (16,777,216). During DMAC operation, the remaining number of
transfers is shown.
The upper eight bits of DMATCR are reserved. They are always read as 0 and the write value
should always be 0.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value: 0
0
0
0
0
0
0
0
-
-
-
-
-
-
-
-
R/W: R
R
R
R
R
R
R
R R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Rev. 1.0, 02/03, page 372 of 1294