SH7760 Datasheet, PDF (246/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

8.5.3 Interrupts
(1) NMI
• Source: NMI pin edge detection
• Transition address: VBR + H'0000 0600
• Transition operations:
The PC and SR contents for the instruction at which this exception is accepted are saved in
SPC and SSR. The R15 contents at this time are saved in SGR.
Exception code H'1C0 is set in INTEVT. The BL, MD, and RB bits are set to 1 in SR, and a
branch is made to PC = VBR + H'0600. When the BL bit in SR is 0, this interrupt is not
masked by the interrupt mask bits in SR, and is accepted at the highest priority level. When the
BL bit in SR is 1, a software setting can specify whether this interrupt is to be masked or
accepted. For details, see section 9, Interrupt Controller (INTC).
NMI()
{
SPC = PC;
SSR = SR;
SGR = R15;
INTEVT = H'0000 01C0;
SR.MD = 1;
SR.RB = 1;
SR.BL = 1;
PC = VBR + H'0000 0600;
}
Rev. 1.0, 02/03, page 196 of 1294