SH7760 Datasheet, PDF (1169/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Module Register Name
Abbrev.
P4
Address
Area 7
Address
Size
Sync
Clock
DMAC
DMA audio source address register 1
DMAATXSAR1 H’FE3C 0060 H’1E3C 0060 32
Pck
DMABRG _{DMA audio destination address register 1 DMAARXDAR1 H’FE3C 0064 H’1E3C 0064 32}
Pck
DMA audio transmit transfer count register 1 DMAATXTCR1 H’FE3C 0068 H’1E3C 0068 32
Pck
DMA audio receive transfer count register 1 DMAARXTCR1 H’FE3C 006C H’1E3C 006C 32
Pck
DMA audio control register 1
DMAACR1
H’FE3C 0070 H’1E3C 0070 32
Pck
DMA audio transmit transfer count register 1 DMAATXTCNT1 H’FE3C 0074 H’1E3C 0074 32
Pck
DMA audio receive transfer count register 1 DMAARXTCNT1 H’FE3C 0078 H’1E3C 0078 32
Pck
DAM USB source address register
DMAUSAR
H'FE3C 0080 H'1E3C 0080 32
Pck
DMA USB destination address register
DMAUDAR
H'FE3C 0084 H'1E3C 0084 32
Pck
DMA USB R/W size register
DMAURWSZ H'FE3C 0088 H'1E3C 0088 32
Pck
DMA USB control register
DMAUCR
H'FE3C 008C H'1E3C 008C 32
Pck
CPG
Frequency control register
FRQCR
H'FFC0 0000 H'1FC0 0000 16
Pck
Clock division register
DCKDR
H'FE0A 0020 H'1E0A 0020 32
Pck
WDT
Module clock control register
Watchdog timer counter
Watchdog timer control/status register
MCKCR
WTCNT
WTCSR
H'FE0A 0024 H'1E0A 0024
H'FFC0 0008 H'1FC0 0008
H'FFC0 000C H'1FC0 000C
32
Pck
8/16*² Pck
8/16*² Pck
Power-down Standby control register
STBCR
H'FFC0 0004 H'1FC0 0004 8
Pck
Standby control register 2
STBCR2
H'FFC0 0010 H'1FC0 0010 8
Pck
Clock stop register 00
CLKSTP00
H'FE0A 0000 H'1E0A 0000 32
Pck
Clock stop clear register 00
CLKSTPCLR00 H'FE0A 0010 H'1E0A 0010 32
Pck
TMU
common
Timer start register
TSTR
H'FFD8 0004 H'1FD8 0004 8
Pck
TMU
Timer constant register 0
Channel 0 _{Timer counter 0}
TCOR0
TCNT0
H'FFD8 0008 H'1FD8 0008 32
Pck
H'FFD8 000C H'1FD8 000C 32
Pck
Timer control register 0
TCR0
H'FFD8 0010 H'1FD8 0010 16
Pck
TMU
Timer constant register 1
Channel 1 _{Timer counter 1}
TCOR1
TCNT1
H'FFD8 0014 H'1FD8 0014 32
Pck
H'FFD8 0018 H'1FD8 0018 32
Pck
Timer control register 1
TCR1
H'FFD8 001C H'1FD8 001C 16
Pck
TMU
Timer constant register 2
Channel 2 _{Timer counter 2}
TCOR2
TCNT2
H'FFD8 0020 H'1FD8 0020 32
Pck
H'FFD8 0024 H'1FD8 0024 32
Pck
Timer control register 2
TCR2
H'FFD8 0028 H'1FD8 0028 16
Pck
Input capture register 2
TCPR2
H'FFD8 002C H'1FD8 002C 32
Pck
Rev. 1.0, 02/03, page 1119 of 1294