SH7760 Datasheet, PDF(364/1345 Page) Renesas Technology Corp – SuperHTM RISC engine

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SH7760 Datasheet, PDF (364/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

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CKIO

Bank

Precharge-sel

Address

CSn

RD/WR

RAS

CASS

DQMn

Tnop (Tnop) Tc1 Tc2 Tc3 Tc4 Tc5 Tc6 Tc7 Tc8 Trw1 Trw1

H/L

c1

H/L

c5

D31âD0

(write)

BS

CKE

DACKn

(SA: IO â memory)

c1 c2 c3 c4 c5 c6 c7 c8

â Single address DMA

â Normal write

Note:

The (Tnop) cycle is inserted only for SA-DMA. The DACKn signal is output as indicated by the solid line.

In the case of a normal write, the (Tnop) cycle is deleted and the DACKn signal is output as indicated by the dotted line.

For DACKn, an example is shown where CHCRn.AL (acknowledge level) = 0 for the DMAC.

Figure 10.24 Burst Write Timing (Same Row Address)

Rev. 1.0, 02/03, page 314 of 1294

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