SH7760 Datasheet, PDF (1269/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Figure 33.27 Synchronous DRAM Normal Read Bus Cycle: ACT + READ Commands,
Burst (RCD[1:0]=01, CAS Latency=3)
Rev. 1.0, 02/03, page 1219 of 1294