SH7760 Datasheet, PDF (1318/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

B. Mode Pin Settings
The MD8–MD0 pin values are input in the event of a power-on reset via the RESET pin.
Table B.1 Clock Operating Modes (SH7760)
Clock
Operating
Mode
External
Pin Combination
MD2 MD1 MD0
PLL1
CPU
PLL2 Clock
Frequency
(vs. Input Clock)
Bus Peripheral
Clock Module Clock
FRQCR
Initial Value
0
0
0
0
On (×12) On 12
3
3
H'0E1A
1
1
On (×12) On 12
3/2
3/2
H'0E2C
2
1
0
On (×6) On 6
2
1
H'0E13
3
1
On (×12) On 12
4
2
H'0E13
4
1
0
0
On (×6) On 6
3
3/2
H'0E0A
5
1
On (×12) On 12
6
3
H'0E0A
6
1
0
Off (×6) Off 1
1/2
1/2
H'0808
Notes: 1. The multiplication factor of PLL1 is solely determined by the clock operating mode.
2. For the ranges input clock frequency, see the description of the EXTAL clock input
frequency (f_EX) and the CKIO clock output (f_OP) in section 33.3.1, Clock and Control
Signal Timing.
Table B.2 Area 0 Memory Map and Bus Width
MD6
0
1
Pin Value
MD4
MD3
0
0
1
1
0
1
0
0
1
1
0
1
Memory Type
Setting prohibited
Setting prohibited
Setting prohibited
MPX interface
Setting prohibited
SRAM interface
SRAM interface
SRAM interface
Bus Width
Setting prohibited
Setting prohibited
Setting prohibited
32 bits
Setting prohibited
8 bits
16 bits
32 bits
Rev. 1.0, 02/03, page 1268 of 1294