SH7760 Datasheet, PDF (1083/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

29.7.3 Pck and Clock Division Ratio Settings
Four types of divided clocks can be used as the clock for A/D conversion. Since the internal
circuit configuration affects the limits of the interface between the analog and digital sections, be
sure to see table 29.5 when setting the input clock and clock division ratio.
Table 29.5 Relationship between Clock Division Ratio and Usable Input Clock Frequency
Clock Division Ratio
Pck/4
Pck/8
Pck/16
Pck/32
Input Clock
18 MHz or lower
34 MHz or lower
34 MHz or lower
34 MHz or lower
29.7.4 Notes on Standby Modes
Before entering hardware standby, module standby, or software standby modes, check that A/D
conversion is not in progress, that is, the ADF bit is 1, or in multi mode or scan mode, clear the
ADST bit to 0 to stop A/D conversion. Note that A/D conversion does not stop immediately. If
module standby or software standby mode is entered without confirming that A/D conversion is
stopped, correct AD converter operation is not guaranteed.
In hardware standby, module standby, or software standby mode, all AD converter registers are
initialized.
Rev. 1.0, 02/03, page 1033 of 1294