SH7760 Datasheet, PDF (1086/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Figure 30.1 shows a block diagram of LCDC.
LCD_CLK
Bck
Pck
Peripheral
bus
Clock
generator
DOTCLK
Register
LCDC
Pallet RAM
4 bytes × 256 entries
DMABRG interface
Power control
Line buffer
2.4 kbytes
LCD_CL1
LCD_CL2
LCD_FLM
LCD_DATA 15–0
LCD_DON
VCPWC
VEPWC
LCD_M_DISP
DMABRG
Figure 30.1 LCDC Block Diagram
30.2 Input/Output Pins
Table 30.1 summarizes the LCDC's pin configuration.
Table 30.1 Pin Configuration
Name
I/O
Function
LCD_DATA15 to 0 Output Data for LCD panel
LCD_DON
Output Display-on signal (DON)
LCD_CL1
Output Shift-clock 1 (STN/DSTN)/horizontal sync signal (HSYNC) (TFT)
LCD_CL2
Output Shift-clock 2 (STN/DSTN)/dot clock (DOTCLK) (TFT)
LCD_M_DISP
Output LCD current-alternating signal/DISP signal
LCD_FLM
Output First line marker/vertical sync signal (VSYNC) (TFT)
VCPWC
Output LCD-module power control (VCC)
VEPWC
Output LCD-module power control (VEE)
LCD_CLK
Input LCD clock-source input
Note: Check the LCD module specifications carefully in section 30.5, Clock and LCD Data
Signal Examples, before deciding on the wiring specifications for the LCD module.
Rev. 1.0, 02/03, page 1036 of 1294