SH7760 Datasheet, PDF (1022/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

27.3 Register Descriptions
The MFI has the following registers. For information on the register addresses and register states
during various processing states, refer to section 32, List of Registers.
Table 27.2 Register Configuration (1)
Register Name
Abbrev. R/W P4 Address
MFI index register
MFIIDX R/W*¹ H’FE2C 0000
MFI general status register
MFIGSR R/W H’FE2C 0004
MFI status/control register
MFISCR R/W*² H’FE2C 0008
MFI memory control register
MFIMCR R/W*⁴ H’FE2C 000C
MFI on-chip interrupt control register MFIIICR R/W H’FE2C 0010
MFI external interrupt control register MFIEICR R/W H’FE2C 0014
MFI address register
MFIADR R/W*⁵ H’FE2C 0018
MFI data register
MFIDATA R/W H’FE2C 001C
MFRAM R/W
Start
H’FE2E 0000
MFRAM R/W
End
H’FE2E 07FF
Area 7 Address Size
H’1E2C 0000 32
H’1E2C 0004 32
H’1E2C 0008 32
H’1E2C 000C 32
H’1E2C 0010 32
H’1E2C 0014 32
H’1E2C 0018 32
H’1E2C 001C 32
H’1E2E 0000 32
Sync
Clock
Pck
Pck
Pck
Pck
Pck
Pck
Pck
Pck
Pck
H’1E2E 07FF 32 Pck
Rev. 1.0, 02/03, page 972 of 1294