SH7760 Datasheet, PDF (1056/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Table 28.4 Register Configuration (2)
Register Name
Instruction register
Abbrev.
SDIR
H-UDI Side
R/W Size
R/W 32
Data register H
Data register L
Interrupt source register
Bypass register
Boundary scan register
SDDR/SDDRH — —
SDDRL
——
SDINT
W*³ 32
SDBPR
R/W 1
SDBSR
R/W —
Initial Value*¹
H’FFFF FFFD (Fixed
value*²)
—
—
H’0000 0000
Undefined
Undefined
Sync Clock
Pck
Pck
Pck
Pck
—
—
Table 28.4 Register Configuration (3)
Register Name
Abbrev.
Power-on
Reset by
RESET
Pin/WDT/
H-UDI
Manual Reset
by RESET Sleep
Pin/WDT/
by Sleep
Multiple
Instruction/
Exception Deep Sleep
Standby
by
Software/
by
Each
Hardware Module
Instruction register
SDIR
H’FFFF*⁴
Retained
Retained
* Retained
Data register H
SDDR/SDDRH Undefined Retained
Retained
Retained
Data register L
SDDRL
Undefined Retained
Retained
Retained
Interrupt source register SDINT
H’0000
Retained
Retained
Retained
Notes: * After exiting hardware standby mode, this LSI enters the power-on reset state by the
RESET pin.
*1. Initialized when the TRST pin is low or the TAP controller is in the Test-Logic-Reset
state.
*2. Always read as the fixed value (H’FFFF FFFD) from the H-UDI side.
*3. Using the H-UDI interrupt command sets the LSB to 1.
*4. Reserved bits are read as undefined values. For details, see each of the register
descriptions.
Rev. 1.0, 02/03, page 1006 of 1294