SH7760 Datasheet, PDF (275/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

9.5 Operation
9.5.1 Interrupt Operation Sequence
The sequence of operations when an interrupt is generated is described below. Figure 9.3 shows a
flowchart of the interrupt operations.
1. The interrupt request sources send interrupt request signals to the interrupt controller.
2. The interrupt controller selects the highest-priority interrupt from the interrupt requests sent,
according to the priority levels set in IPRA to IPRD and INTPRI00 to INTPRI0C. Lower-
priority interrupts are held pending. If two of these interrupts have the same priority level, or if
multiple interrupts occur within a single module, the interrupt with the highest priority
according to table 9.4 is selected.
3. The priority level of the interrupt selected by the interrupt controller is compared with the
interrupt mask level (IMASK3 to IMASK0) in SR of the CPU. If the request's priority level is
higher than the level in bits IMASK3 to IMASK0, the interrupt controller accepts the interrupt
and sends an interrupt request signal to the CPU.
4. The CPU accepts an interrupt between instructions.
5. The interrupt source code is set in the interrupt event register (INTEVT).
6. The contents of the status register (SR) and program counter (PC) are saved to SSR and SPC,
respectively. The R15 contents at this time are saved in SGR.
7. The block bit (BL), mode bit (MD), and register bank bit (RB) in SR are set to 1.
8. The CPU jumps to the start address of the interrupt-related exception handling routine (the sum
of the value set in the vector base register (VBR) and H'0000 0600).
The exception handling routine may branch with the INTEVT value as its offset in order to
identify the interrupt source. This enables it to easily branch to the handling routine for the
particular interrupt source.
Notes: 1. In this LSI, the interrupt mask level bits (IMASK3 to IMASK0) in the status register
(SR) of the CPU are not changed by acceptance of an interrupt.
2. Clear the interrupt source flag during the interrupt handling routine.
To ensure that the cleared interrupt source is not inadvertently accepted again, read the
interrupt source flag after it has been cleared, wait for the interval shown in table 9.8,
and then clear the BL bit or execute an RTE instruction.
3. For some interrupt sources, the interrupt masks (INTMSK00 and INTMSK04) must be
cleared using INTMSKCLR00 and INTMSKCLR04.
Rev. 1.0, 02/03, page 225 of 1294