SH7760 Datasheet, PDF (1290/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

CKIO
A25-A0
CSn
RD/WR
RD
D31-D0
(read)
WEn
BS
TS1
T1
T2
TH1
t_AD
t_CSD
t_RWD
t_RSD
t_RSD
t_WED1
t_BSD
t_RDS
t_WEDF
t_BSD
t_AD
t_CSD
t_RWD
t_RSD
t_RDH
t_WED1
RDY
DACKn
(SA: IO memory)
t_DACD
DACKn
(DA)
t_DACD
t_DACD
t_DACD
Notes: IO : Dack device
SA : Single address DMA transfer
DA : Dual address DMA transfer
DACK set to active-high
Figure 33.48 Memory Byte Control SRAM Bus Cycle: Basic Read Cycle
(No Wait, Address Setup/Hold Time Insertion, AnS=1, AnH=1)
Rev. 1.0, 02/03, page 1240 of 1294