SH7760 Datasheet, PDF (859/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Bit Name Initial Value R/W
Description
15 to 0 TCNTR[15:0] All 0
R/W*
Indicates the value of 16 bit Free Running
Timer
Note: * The register can be cleared by the Compare Match condition.
22.5.16 Timer Control Register (CANTCR)
CANTCR is a 16-bit read/write register and provides functions to control the operation of the
Timer.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
TCR15 - TCR13 TCR12 TCR11 -
-
-
-
- TPSC5 TPSC4 TPSC3 TPSC2 TPSC1 TPSC0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R R/W R/W R/W R
R
R
R
R R/W R/W R/W R/W R/W R/W
Bit
Bit Name Initial Value R/W Description
15
TCR15
0
R/W Enable Timer
When this bit is set, the timer is running. When
this bit is cleared the timer completes the current
cycle (notified by Timer overrun or a compare
match on CANTCMR) and is cleared to 0.
0: Timer stops running and is cleared at the end
of the current cycle.
1: Timer is running.
14
—
0
—
Reserved
The write value should always be 0. The read
value is not guaranteed.
13
TCR13
0
R/W TimeStamp Control for Reception
Specifies if the Timestamp in the message control
of each Mailbox is recorded at the StartOfFrame
(SOF) or EndOfFrame (EOF).
0: Timestamp is recorded at the SOF of every
message received.
1: Timestamp is recorded at the EOF of every
message received.
Rev. 1.0, 02/03, page 809 of 1294