SH7760 Datasheet, PDF (548/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Note: * Software standby mode can be cleared by an IRQ4 or IRQ5 interrupt, but not by an IRQ6
or IRQ7 interrupt.
(a) Exit by interrupt
A hot start can be performed by means of the on-chip WDT. When an NMI, IRL, IRQ, or
GPIO interrupt is detected, the WDT starts counting. After the count overflows, clocks are
supplied to the entire LSI, software standby mode is exited, and the STATUS1 and
STATUS0 pins both go low. Interrupt exception handling is then executed, and the code
corresponding to the interrupt source is set in INTEVT. In standby mode, interrupts are
accepted even if the BL bit in the SR register is 1, and so, if necessary, SPC and SSR
should be saved to the stack before executing the SLEEP instruction.
The phase of the CKIO pin clock output may be unstable immediately after an interrupt is
detected, until software standby mode is exited.
(b) Exit by reset
Software standby mode is exited by means of a reset (power-on or manual) via the RESET
pin. The RESET pin should be held low until clock oscillation stabilizes. The internal clock
continues to be output at the CKIO pin.
(3) Clock Pause Function
In software standby mode, it is possible to stop or change the frequency of the clock input
from the EXTAL pin. This function is used as follows.
(a) Enter software standby mode following the transition procedure described above.
(b) When software standby mode is entered and the LSI's internal clock stops, a low-level
signal is output at the STATUS1 pin, and a high-level signal at the STATUS0 pin.
(c) The input clock is stopped, or its frequency changed, after the STATUS1 pin goes low and
the STATUS0 pin high.
(d) When the frequency is changed, input an NMI interrupt after the change. When the clock is
stopped, input an NMI interrupt after applying the clock.
(e) After the time set in the WDT, clock supply begins inside the LSI, the STATUS1 and
STATUS0 pins both go low, and operation is resumed from interrupt exception handling.
14.3.4 Module Standby Function
(1) Transition to Module Standby Function
Setting 1 to the MSTP6 to MSTP4 and MSTP2 bits in STBCR and STBCR2, and the CSTP31
to CSTP0 bits in CLKSTP00 enables the clock supply to the corresponding peripheral modules
to be halted. Use of this function allows power consumption in sleep mode to be further
reduced.
In the module standby state, the peripheral module external pins retain their states prior to
halting of the modules, and most registers retain their states prior to halting of the modules.
Rev. 1.0, 02/03, page 498 of 1294