SH7760 Datasheet, PDF (626/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

17.4 Operation
17.4.1 Overview
The SCIF can carry out serial communication in asynchronous mode, in which synchronization is
achieved character by character and in synchronous mode, in which synchronization is achieved
with clock pulses. For details on asynchronous mode, see section 17.4.2, Operation in
Asynchronous Mode.
128-stage FIFO buffers are provided for both transmission and reception, reducing the CPU
overhead, and enabling fast and continuous communication to be performed.
SCIF_RTS and SCIF_CTS signals are also provided as modem control signals.
The serial transfer format is selected using SCSMR, as shown in table 17.4. The SCIF clock
source is determined by the combination of the C/A bit in SCSMR and the CKE1 and CKE0 bits
in SCSCR, as shown in table 17.5.
Asynchronous Mode:
• Data length: Choice of 7 or 8 bits
• Choice of parity addition and addition of 1 or 2 stop bits (the combination of these parameters
determines the transfer format and character length)
• Detection of framing errors, parity errors, receive-FIFO-data-full state, overrun errors, receive-
data-ready state, and breaks, during reception
• Indication of the number of data bytes stored in the transmit and receive FIFO registers
• Choice of internal or external clock as SCIF clock source
When internal clock is selected: The SCIF operates on the baud rate generator clock and can
output a clock with frequency of 16 times the bit rate.
When external clock is selected: A clock with a frequency of 16 times the bit rate must be
input (the on-chip baud rate generator is not used).
Synchronous Mode:
• Data length: Fixed at 8 bits
• Detection of overrun errors during reception
• Choice of internal or external clock as SCIF clock source
When internal clock is selected: The SCIF operates on the baud rate generator clock and a
serial clock is output to external devices.
When external clock is selected: The on-chip baud rate generator is not used and the SCIF
operates on the input serial clock.
Rev. 1.0, 02/03, page 576 of 1294