SH7760 Datasheet, PDF (1111/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit Bit Name
7
OFFE3
6
OFFE2
5
OFFE1
4
OFFE0
3
OFFF3
2
OFFF2
1
OFFF1
0
OFFF0
Initial Value R/W
0
R/W
0
R/W
0
R/W
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
Description
LCDC Power-Off Sequence Period
Sets the period from VEPWC negation to stopping
output of the display data (LCD_DATA) and timing
signals (LCD_FLM, LCD_CL1, LCD_CL2, and
LCD_M_DISP) in the power-off sequence of the
LCD module in frame units.
Specify a value of (the period) −1.
This period is the (e) period in figures 30.4 to 30.7,
Power-Supply Control Sequence and States of the
LCD Module.
LCDC Power-Off Sequence Period
Sets the period from stopping output of the display
data (LCD_DATA) and timing signals (LCD_FLM,
LCD_CL1, LCD_CL2, and LCD_M_DISP) to
VCPWC negation in the power-off sequence of the
LCD module in frame units.
Specify a value of (the period) −1.
This period is the (f) period in figures 30.4 to 30.7,
Power-Supply Control Sequence and States of the
LCD Module.
30.3.19 LCDC Control Register (LDCNTR)
LDCNTR specifies start and stop of display by the LCDC.
The LCDC begins display when a value of 1 is input to both the DON2 bit and the DON bit.
Power is then supplied to the LCD module in accordance with the sequence set by the LDPMM
and LDCNTR. The sequence ends when the LPS[1:0] value changes from B'00 to B'11. Do not
make any action to the DON bit until the sequence ends.
The LCDC stops display when a value of 0 is input to the DON bit. Power to the LCD module is
cut off in accordance with the sequence set by the LDPMMR and LDCNTR. The sequence ends
when the LPS[1:0] value changes from B'11 to B'00. Do not make any action to the DON bit until
the sequence ends.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
- DON2 -
-
- DON
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R R/W R
R
R R/W
Rev. 1.0, 02/03, page 1061 of 1294