SH7760 Datasheet, PDF (547/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

14.3.2 Deep Sleep Mode
(1) Transition to Deep Sleep Mode
If a SLEEP instruction is executed when the STBY bit in STBCR is cleared to 0 and the DSLP
bit in STBCR2 is set to 1, the chip switches from the program execution state to deep sleep
mode. After execution of the SLEEP instruction, the CPU halts but its register contents are
retained. Except for the DMAC, peripheral modules continue to operate. The clock continues
to be output to the CKIO pin, but all bus access (including auto refresh) stops. When using
memory that requires refreshing, select self-refreshing mode prior to making the transition to
deep sleep mode. Terminate DMA transfers prior to making the transition to deep sleep mode.
If you make a transition to deep sleep mode while DMA transfers are in progress, the results of
those transfers cannot be guaranteed.
In deep sleep mode, a high-level signal is output at the STATUS1 pin, and a low-level signal at
the STATUS0 pin.
(2) Exit from Deep Sleep Mode
As with sleep mode, deep sleep mode is exited by means of an interrupt (NMI, IRL, IRQ,
GPIO, or peripheral module) or a reset.
14.3.3 Software Standby Mode
(1) Transition to Software Standby Mode
If a SLEEP instruction is executed when the STBY bit in STBCR is set to 1, the chip switches
from the program execution state to software standby mode. In software standby mode, the
clock and peripheral modules halt as well as the CPU. Clock output from the CKIO pin is also
stopped.
The CPU and cache register contents are retained. Some peripheral module registers are
initialized.
The procedure for a transition to software standby mode is shown below.
(a) Clear the TME bit in WTCSR of the WDT to 0, and stop the WDT.
Set the initial value for up counting in WTCNT of the WDT, and set the clock to be used
for up counting in bits CKS2 to CKS0 in WTCSR.
(b) Set the STBY bit in STBCR to 1, then execute a SLEEP instruction.
(c) When software standby mode is entered and the LSI's internal clock stops, a low-level
signal is output at the STATUS1 pin, and a high-level signal at the STATUS0 pin.
(2) Exit from Software Standby Mode
Software standby mode is exited by means of an interrupt (NMI, IRL, IRQ*, or GPIO) or a
reset via the RESET and MRESET pins.
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