SH7760 Datasheet, PDF (876/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

23.3.1 Control Register (SPCR)
SPCR is a 32-bit readable/writable register that controls the transfer data of shift timing and
specifies the clock polarity and frequency.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
-
-
-
-
-
-
-
Initial value: -
-
-
-
-
-
-
R/W: R
R
R
R
R
R
R
8
7
6
5
4
3
2
1
0
-
FBS CLKP IDIV CLKC4 CLKC3 CLKC2 CLKC1 CLKC0
-
0
0
0
0
0
0
0
0
R R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name
31 to 8 
Initial Value R/W
All 
R
7
FBS
0
R/W
6
CLKP
0
R/W
Description
Reserved
These bits are always read as an undefined
value. The write value should always be 0.
First Bit Start
Controls the timing relationship between each bit
of transferred data and the serial bit clock.
0: The first bit transmitted from the HSPI module
is set up such that it can be sampled by the
receiving device on the first edge of HSPI_CLK
after the HSPI_CS pin goes low. Similarly the
first received bit is sampled on the first edge of
HSPI_CLK after the HSPI_CS pin goes low.
1: The first bit transmitted from the HSPI module
is set up such that it can be sampled by the
receiving device on the second edge of
HSPI_CLK after the HSPI_CS pin goes low.
Similarly the first received bit is sampled on the
second edge of HSPI_CLK after the HSPI_CS
pin goes low.
Serial Clock Polarity
0: HSPI_CLK signal is not inverted and so is low
when inactive.
1: HSPI_CLK signal is inverted and so is high
when inactive.
Rev. 1.0, 02/03, page 826 of 1294