SH7760 Datasheet, PDF (1256/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

33.3.2 Control Signal Timing
Table 33.6 Control Signal Timing
(V_DDQ= 3.0 to 3.6V, V_DD= 1.5V, T_a= −40 to 85°C, C_L= 30pF, PLL2 on)
Item
BREQ setup time
BREQ hold time
BACK delay time
Bus tri-state delay time
Bus tri-state delay time to standby mode
Bus buffer on time
Bus buffer on time from standby
STATUS 0/1 delay time
STATUS 0/1 delay time to standby
Note: t_cyc shows 1 cycle time of a CKIO clock.
Symbol
t_BREQS
t_BREQH
t_BACKD
t_BOFF1
t
BOFF2
t_BON1
t_BON2
t_STD1
t_STD2
Min.
3
1.5







Max.


6
12
2
12
2
6
2
Unit
ns
ns
ns
ns
t
cyc
ns
t_cyc
ns
t_cyc
Figure
33.15
33.15
33.15
33.15
33.16
33.15
33.16
33.16
33.16
CKIO
BREQ
BACK
A[25:0], CSn, BS,
RD/WR, CE2A, CE2B,
RAS, WEn, RD, CASn
t_BREQH
t_BREQS
t_BREQH
t_BREQS
t_BACKD
t_BACKD
t_BOFF1
t_BON1
Figure 33.15 Control Signal Timing
Rev. 1.0, 02/03, page 1206 of 1294