SH7760 Datasheet, PDF (316/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Initial
Bit
Name Value R/W
31 to 2 
All 0
R
1
CSH1 0
R/W
0
CSH0 0
R/W
Description
Reserved
These bits are always read as 0, and the write value
should always be 0.
CS Hold Cycle Setting
Specifies the number of wait cycles to be inserted during
data hold time.
Wait cycles to be inserted
00: 0
01: 1
10: 2
11: 3
10.5.9 Memory Control Register (MCR)
MCR is a 32-bit readable/writable register that specifies RAS and CASS timing, burst control,
address multiplexing, and refresh control for synchronous DRAM (areas 2 and 3).
Write bits 31 to 3 when making the initial settings after a power-on reset and do not modify the
settings from then onward. When writing to bits RFSH and RMODE, write the same values
without changing other bits. When using synchronous DRAM, do not access areas 2 and 3 before
register initialization is complete.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MR
RASD _SET TRC2 TRC1 TRC0
-
-
-
-
- TPC2 TPC1 TPC0 - RCD1 RCD0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R R R R R R/W R/W R/W R R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
TRWL TRWL TRWL TRAS TRAS TRAS
2
1
0
2
1
0
-
SZ1
SZ0
AMX
EXT
AMX2 AMX1 AMX0 RFSH
RM
ODE
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R
Rev. 1.0, 02/03, page 266 of 1294